The escalating requirements for high density and performance associated with ultra-large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra-large scale integration technology. High density demands for ultra-large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. This problem is exacerbated in manufacturing semiconductor devices having sub-half micron technology.
In accordance with conventional practices, an anti-reflective coating (ARC) is utilized in sub-half micron photolithography to minimize notches caused by reflections. In accordance with such conventional practices, design features of about 0.35 microns are printed using i-line lithographic techniques. Typically, an i-line photoresist is applied on a polysilicon layer, with an organic ARC disposed therebetween. This type of arrangement is routinely utilized in the manufacture of semiconductor devices, particularly for forming a gate electrode, wherein the gate electrode image is transferred to the polysilicon layer employing an anisotropic plasma etching technique. Thus, in order to pattern the polysilicon layer into a gate electrode, the ARC must be etched prior to etching the polysilicon layer to form the gate electrode.
Conventional practices involve the use of etching recipes based on fluorinated hydrocarbons, such as CF.sub.4 /O.sub.2 and CHF.sub.3 /O.sub.2 /Ar to etch the ARC. After etching the ARC, the polysilicon layer is conventionally etched employing a recipe such as Cl.sub.2 /Br.sub.2 with or without BCl.sub.3. Both the ARC and polysilicon layers are etched in a gaseous plasma.
It is extremely difficult, if not impossible, to etch a composite comprising of a polysilicon underlayer and an ARC thereon in a single chamber. In addition, the etch profiles of gate electrodes formed on a semiconductor substrate lack uniformity, notwithstanding their formation during the same etching procedure.
Accordingly, there exists a need for a method of manufacturing a semiconductor device wherein a composite of a polysilicon underlayer and an ARC thereon is etched in a single chamber to accurately pattern gate electrodes exhibiting uniform etch profiles.